Integrated circuit design is an increasingly complex process and relies heavily on the use of computer-based tools. As designs get larger, and the critical dimension in fabrication processes shrink, the problem of evaluating and optimizing the physical design is becoming more burdensome. Current generation integrated circuits are being designed for processes with features sizes of 90 nanometers, 65 nanometers and smaller. Technology with feature sizes in this range are sometimes referred to as “deep-submicron” or “nanometer” technologies.
In nanometer technologies, many electrical properties that were previously second and third order effects have come to play a major role in determining circuit performance and power consumption. One reason for this is that shrinking geometries have caused the variability of design parameters to increase. For example, interconnect geometry parameters such as wire thickness and resistivity have an increasingly higher variation as a percentage of the total thickness and resistivity. Variability can be exhibited both inter-chip and intra-chip. Variability affects both device parameters and interconnect parameters and directly determines the margin and achievable yield of an integrated circuit design.
Variability comes from many sources. We can generally classify the source of variations into four groups: environmental, manufacturing, reliability and operational.
a. Environmental Variations
Environmental variations arise during the operation of a chip and include both global (inter-chip) and local (intra-chip) environmental variations. Global environmental variations include variations in chip ambient temperature and supply voltage. Local environmental variations are caused by variations in power supply, local coupling, and temperature across the chip.
Global environmental variations such as ambient temperature and supply voltage can change the electrical characteristics of devices. Worst case timing has been traditionally modeled using parameters characterizing a low voltage, a slow process and a high temperature. This approach is not always sufficient for nanometer technologies because such processes sometimes exhibit inverted temperature behavior, whereby the worst timing occurs at a low temperature rather than a high temperature. This inverted temperature behavior can be traced to transistor current-voltage (IV) characteristics. The transistor saturation current is dominated by: temperature mobility dependency above the temperature neutral point, and temperature threshold dependency below the temperature neutral point. The temperature inversion effect typically varies for each library cell and may get worse when lower operating voltages are used.
Local environmental variations are caused by the operation of the chip and include such local effects as:
Device voltage variations due to voltage drop (IR drop) and ground bounce
Delay and slew variations due to crosstalk
Input pin capacitance variation due to slew and state dependency
Device performance degradation due to negative bias temperature instability
IR drop and crosstalk induced variations are more prominent in nanometer technologies than in previous technologies. Previously, the capacitance seen at the input of a CMOS cell has been considered independent of all factors external to the cell. The increasing drain-to-gate capacitance has changed this assumption. Now it is often important to consider the Miller Capacitance effect, making the effective input capacitance a function of the load capacitance and the input slew. Effective pin capacitance usually increases with slew and decreases with cell output load. The dependency of input capacitance on the state of the cell adds further modeling complications.
b. Manufacturing Variations
Manufacturing variations result in permanent structural device and interconnect variations. These variations arise due to processing and masking limitations, and result in random or spatially varying deviations from designed parameter values. Manufacturing variations affect both interconnect and device characteristics and are experienced both globally (inter-chip) and locally (intra-chip).
Global manufacturing variations include global geometric variations in device and interconnect as well as material parameter variation in device and interconnect. Device geometric variations such as effective channel length variation and film thickness variation can result in systematic chip-to-chip threshold voltage (Vt) and leakage current variations. This threshold voltage variation affects delay and leakage power. Similarly deviations in the width of lower metal layers due to proximity and lithographic effects can directly impact line resistance as well as coupling capacitance. Global variation in metal and dielectric thickness also leads to global resistance and capacitance variations.
Local manufacturing variations include device and interconnect geometry variations due to local layout as well as random material parameter variation. Device effective channel length has some plasma etch dependencies (which depends on local layout) and it manifests itself in the form of local threshold voltage (Vt) variations. Interconnect local geometric variations include local layout dependent width and spacing variation, dishing and erosion of metal, as well as dielectric thickness variation.
Interconnect line width and spacing deviations arise primarily due to photolithographic and etch dependencies. For lower metal layers, lithographic and proximity effects may be important while at other levels aspect ratio dependent etch effects, which depend on local layout can be significant. These deviations directly impact interconnect parasitics and result in performance and signal integrity degradation.
Significant local metal thickness variation (10–20 percent) has been observed for nanometer copper technologies resulting in dishing and erosion. Similarly, chemical mechanical planarization (CMP) can introduce strong dielectric thickness variations across the die. Selective process bias (SPB) based on width and spacing to adjacent metal has been used to address local layout effect on interconnect. In nanometer technologies, dishing and erosion effects need to be modeled as well.
FIG. 1 is an illustration of one aspect of the problem addressed by the present invention. FIG. 1 shows local and global variation of inter-layer dielectric thickness across a wafer. Each square in FIG. 1 represents a single die and the entire surface illustrated represents a single wafer. The local variation of inter-layer dielectric thickness is represented by the vertical range of a single square, while the global variation is represented by the vertical range of the entire surface.
c. Reliability Variations
Reliability variations are caused by various wear-out mechanisms, in which device performance degrades over time. It should be ensured that the degradation does not cause functional or performance failures during or after the degradation. In nanometer technologies, negative bias temperature instability (NBTI) is expected to cause significant P-transistor performance degradation over device lifetime. It degrades the threshold voltage (Vt) as well as drive current of the P transistors. This is especially problematic for pull-up devices and can cause larger delays.
In some cases, it is desirable to model wear-out mechanisms for clock signals (which experience more switching over the lifetime of the chip) differently than for ordinary logic signals. Reliability variations can be modeled as either global variations (considering new and old characteristics globally as different operating points), or as local variations (considering old and new characteristics locally as different device characteristics), or some combination of the two.
d. Operational Variations
Operational variability refers to different operating modes of an IC. For example, an IC may be designed to work in functional mode, test mode, sleep mode, and power-off mode. Different modes come with different design constraints that must be simultaneously analyzed for fast design closure.
e. Traditional Approaches
Traditionally, variability has been handled through two-corner analysis. We use the term “corner” to refer to any combination of process, voltage and temperature (PVT), as well as other environmental, manufacturing or reliability factors. In a traditional two-corner analysis, late (i.e., setup) analysis is carried out for parameters characterizing a weak process, a minimum voltage, and a high temperature, and early (i.e., hold) analysis is carried out for parameters characterizing a strong process, a maximum voltage, and a low temperature. In such traditional approaches, nominal interconnect models are generally used everywhere and a bit of margin is used to cover up uncertainty.
One limitation of a traditional two-corner analysis is that signal integrity problems may be worse at other corners. For example, noise problems may only show themselves at a strong process and high temperature conditions.
Another problem with the traditional approaches is that they model certain variations as uncertainty when they are actually deterministic. In fact, a substantial portion of local variability is design and layout dependent and therefore deterministic. Similarly, many global variability sources (e.g., ambient temperature) can be known in advance and deterministically modeled. Operational variability is always deterministic.
Ideally, deterministic variability impact can be assessed and tuned out of the design. However, lack of modeling resources often transform variability into uncertainty and effectively convert systematic variation into randomized one.
Treating deterministic variability as uncertainty is both pessimistic and risky at the same time. It is pessimistic as is the nature of bounding methods that seek to deliver guarantees on the earliest and latest arrival times. Yet, it is risky because it is not possible to conduct a bounding analysis using only two corners.
Traditional methods require users to run each design variability corner individually and verify performance. At most, two-corner single-mode support is implemented in existing solutions. Thus, users are required to ping-pong between each variability corner and between different modes to fix all the timing paths in all the corners.
Another approach, statistical timing, has been proposed by some as a solution for handling variability. However, verifiable statistical device and interconnect models are not yet available. Also, there are significant hurdles involved in getting library vendors and designers to accept statistical timing analysis.
Thus, there is a need for a convergent method to handle variability in an integrated fashion to enable simultaneous analysis and optimization of all the different variability effects. Such a comprehensive variability solution is desirable in analysis and implementation tools for designing nanometer ICs in order to minimize systematic yield loss due to variability and achieve yields near defect-density limits.